/*
 * @Author: lc
 * @Date: 2023-11-06 16:49:00
 * @LastEditors: LC 1774939529@qq.com
 * @LastEditTime: 2024-04-12 22:16:53
 * @FilePath: /display_d_tube/SIM/sim_DT.v
 * @Description: 例化测试程序
 * 
 * Copyright (c) 2023 by ${git_name_email}, All Rights Reserved. 
 */
`timescale 10ns/10ns

//`include "../RTL/top.v"

module sim_DT ();
    reg clk_50Mhz;
    reg rst_n;
    wire OE_n;
    wire shift_clock_cp;
    wire storage_clock_8div_cp;
    wire data_s;
    
    initial begin
        clk_50Mhz = 1'b0;
        rst_n = 1'b0;
        #10000; rst_n = 1'b1;
    end

    always #1 clk_50Mhz = !clk_50Mhz;

    top u_top(
        .clk_50Mhz                  (clk_50Mhz             ),
        .rst_n                      (rst_n                 ),
        .OE_n                       (OE_n                  ),
        .shift_clock_cp             (shift_clock_cp        ),
        .storage_clock_8div_cp      (storage_clock_8div_cp ),
        .data_s                     (data_s                )
    );
	
endmodule
